The GTFPGA Unit, a powerful and versatile hardware platform capable of performing highly dense computations in parallel with the RTDS Simulator, is a rack-mountable enclosure housing a Xilinx Virtex-7 FPGA board. The GTFPGA Unit is interfaced with the RTDS Simulator via an optical fibre cable connected from the rear of the GTFPGA Unit to a NovaCor chassis or rack-mounted PB5 Processor Card participating in the simulation. The GTFPGA Unit has versatile functionality, with different firmwares that can be run on the hardware for different purposes. Additional functionality for the GTFPGA Unit is currently under development.
Modular Multilevel Converter (MMC) Simulation
Modular Multilevel Converters (MMC) offer many advantages compared to conventional thyristor based schemes and are becoming widely used in HVDC and FACTS applications. They also present significant challenges for modeling with Electro-Magnetic Transient (EMT) simulation techniques. RTDS Technologies has developed a number of models to overcome these challenges. The models are small timestep sub-network components which allows great flexibility of configuration as well as very low loop delay between the real time simulation and external controls. The GTFPGA Unit can be used to run detailed models for MMC-based valves, or capacitor voltage balancing and firing pulse control for MMC-based valves.
The RSCAD component library contains two FPGA-based MMC valve models which must be run on the GTFPGA Unit rather than a rack-mounted processor card due to their calculation density. These models are the Unified Model (U5) and the Generic Model (GM). The RSCAD library also contains a model for capacitor voltage balancing and firing pulse control for MMC-based valves.
Generic Model (GM)
The GM is the most detailed MMC valve model available for the RTDS Simulator. The user can model up to 2 valve legs on one GTFPGA Unit. Each valve leg can include up to 1024 SMs. Half bridge, full bridge, and mixed (half and full) configurations are supported. All possible IGBT firing states are considered. The GM supports individual IGBT firing, individual SM capacitances, customized topologies, and internal valve to ground faults. The GM also supports the addition of a damping SM.
Unified Model (U5)
Using U5, the user can model up to 6 valve legs on one GTFPGA Unit. Each valve leg can include up to 512 submodules (SMs). Both half and full bridge configurations are supported. Normal firing states are considered (blocked, positive inserted, negative inserted, and bypassed). Internal faults can be simulated, but not at the IGBT level. The U5 model also supports the addition of a damping SM.
When operating as the capacitor voltage balancing and firing pulse control for the modelled valves, the GTFPGA Unit can be configured to control up to three valve legs with a maximum of 512 submodules each. Therefore, one GTFPGA Unit would be required for control of a 3-phase STATCOM, or two GTFPGA Units could control one terminal of an MMC-based HVDC scheme.
The GTFPGA Units representing the valves are connected to the GTFPGA Units containing the firing pulse controls via optical fibre. The valve models calculate the valve current and the capacitor voltage for each submodule and send the information to the controller. The control in turn provides the firing pulses for each submodule. The signal exchange uses a standard high-speed serial protocol, Aurora, which can be adopted and used for the connection of any external controller.
IEC 61850 Sampled Values Output
Available in RSCAD V5 or higher, the GTFPGA-SV component provides IEC 61850-9-2LE and IEC 61869-9 Sampled Values (SV) communications using the GTFPGA Unit hardware. The use of dedicated FPGA-based hardware significantly increases the number of SV data streams that can be output from the RTDS Simulator. When being used for this purpose, the GTFPGA Unit can be connected to external IEDs through the sixteen Ethernet ports on the front of each unit.
When using IEC 61850-9-2LE configuration, the GTFPGA Unit is able to simultaneously transmit up to:
- 16 data streams for up to 4 current and 4 voltage channels, at a rate of 80 samples/cycle (1 ASDU) or 256 samples/cycle (8 ASDU)
When using IEC 61869-9 configuration, based on the Chinese National Standard for SV merging units, the GTFPGA is able
to simultaneously transmit up to :
- 16 data streams for up to 24 quantities, at a rate of 80 samples/cycle (1 ASDU), 96 samples/cycle (1 ASDU), or 4,800 Hz (2 ASDU)
- 16 data streams for up to 9 quantities, at a rate of 256 samples/cycle (8 ASDU) or 14,400 Hz (6 ADSU)
In IEC 61869-9 mode, the quantities can be currents, voltages, or time-delay. The time-delay channel is the first channel in a Chinese National Standard merging unit SV data stream.
The GTSYNC Synchronization Card is required when using the GTFPGA-SV component. The GTSYNC synchronizes the SV timestamps to an external 1PPS signal from a synchronized time source. When being used for SV, the GTFPGA Unit cannot be connected to GPC cards or older processor cards, and is only compatible with the NovaCor and PB5 based simulators.