Introducing the Universal Converter Model for enhanced real-time power electronics simulation

The RTDS Simulator was originally developed for the closed-loop testing of HVDC controls in the late 1980s, so the representation of line commutated converter (LCC) valves was central to its capabilities. In 2005, the simulation of voltage source converters (VSCs) at timesteps of 1.4 – 3.75 µs was made possible by advances in processing technology, and the RTDS Simulator’s Small Timestep environment was introduced. The Small Timestep allows for freely configurable power electronics simulation running on a dedicated processor in parallel to the main simulation. This is generally achieved via the L/C discrete circuits switching method (“L/C switching”), which is an established approach to representing changes in switching state without requiring refactorization of the network admittance matrix in each small timestep. However, there are challenges to this approach:

• It is well known that the L/C switching method causes artificial switching losses associated with abruptly switching from a small inductor (switch ON) to a small capacitor (switch OFF) model. At switching rates in excess of 3-5 kHz, these artificial losses render the model inaccurate.
• The L/C representation can introduce current and voltage oscillation that can appear as noise on the output waveforms.
• The impedance of the switch is frequency dependent, which limits its operational bandwidth. This places a limitation on the timestep – it must be lower than 3.75 µs in order to ensure that that the ON/OFF impedance ratio is sufficiently large.

To address these issues, resistively-switched converter models are also available in the Small Timestep, but they are decoupled from the surrounding network via a travelling wave interface, and matrix refactorization for all possible switching states are pre-calculated and stored before the simulation case is run. The resistively-switched models are not subject to the same switching frequency maximums as the L/C switched models, but this approach also has its drawbacks:

• If parameters are not selected properly, the interface transmission line adds series inductance and shunt capacitance to the system, which can cause noise and oscillation.
• Due to memory limitations, there is a very limited number of switches that can be represented resistively.

The Small Timestep environment was used successfully for many years by leading developers, manufacturers, and implementers of power electronic controls who use the RTDS Simulator for closed-loop testing.